The present invention relates to a channel switching system and, more particularly, to a channel switching system which can switch a regular channel and a stand-by channel of a digital radio communication system without generation of a bit error by using a synchronizing switch circuit provided at an output of a reception signal processing circuit of a receiving terminal station without using a frame sync signal.
In a conventional broad-band digital radio communication system of, e.g., a microwave band, a channel switching system for instantaneously switching a regular channel and a stand-by channel by using a synchronizing switch circuit provided at a receiving terminal station is used for maintenance of a channel and as a countermeasure against fading.
In the above conventional channel switching system, in order to switch a regular channel to a stand-by channel, a multiplexed digital signal input from a digital multiplexing unit of a transmitting terminal station is converted from a bipolar code to a unipolar code by a B/U converter. Thereafter, a frame sync signal, a monitor control signal, and the like for monitoring a radio section are inserted in the multiplexed digital signal by a transmission signal processing circuit according to speed conversion, and then, the multiplexed digital signal is supplied parallelly to the regular channel and the stand-by channel through a transmission signal distribution circuit and a transmission signal switch circuit. Two digital signals received through the regular and stand-by channels and demodulated in the receiving terminal station are switched without generation of bit error by a synchronizing switch circuit provided between the frame sync circuit and the reception signal processing circuit of the regular channel after a difference between receiving timings is adjusted using frame sync signals respectively detected from the regular and stand-by channels.
In this system, however, a switching time is prolonged because of a frame sync error generated in the stand-by channel when a transmission signal of the regular channel is parallelly supplied to the stand-by channel. In addition, units which can be switched without generation of bit error are only radio units ranging from a radio transmitting unit including a modulator to a radio receiving unit including a demodulator and does not include the B/U converter, the transmission signal processing circuit, and the reception signal processing circuit. As a system for eliminating the above drawbacks, the present applicant has proposed a channel switching system which could switch a channel section from the B/U converter of the transmitting terminal station to the reception signal processing circuit of the receiving terminal station without generating the frame sync error during switching. FIG. 1 exemplifies an arrangement of this channel switching system, in which only one stand-by channel and one regular channel are shown for the sake of descriptive convenience.
In FIG. 1, a multiplexed digital signal 100 from a digital multiplexing unit (not shown) is supplied to a modulator of a transmitting unit (not shown) through a split circuit 1, a B/U converter 2, and a transmission signal processing circuit 3 and transmitted to the receiving terminal station through a regular channel REG. A reception digital signal demodulated by a demodulator of a receiving unit (not shown) is supplied to a reception signal processing circuit 5 through a frame sync circuit 4, and the frame sync signal, the monitor control signal, and the like inserted at the transmitting terminal station are removed by reverse speed conversion therein. Thereafter, the reception digital signal is supplied to a U/B converter 7 through a synchronizing switch circuit 6, converted into a bipolar code therein and then is supplied as a multiplexed digital signal 101 to a digital multiplexing unit (not shown) through a switch 8.
On the other hand, during a normal operation, a monitor digital signal 102 generated by a pilot generator 9 is supplied to a stand-by channel PROT through a switch 10, a B/U converter 2a, and a transmission signal processing circuit 3a. A reception digital signal received at the receiving terminal station is supplied to a pilot detector 12 through a frame sync circuit 4a, a reception signal processing circuit 5a, a distribution circuit 11, a U/B converter 7a, and the switch 8, thereby monitoring a channel state.
In order to switch the regular channel REG to the stand-by channel PROT, the switch 10 at the transmitting terminal station is operated, and the multiplexed digital signal 100 split by the split circuit 1 is supplied to the stand-by channel PROT parallelly to the regular channel REG. Then, after bit timings of a digital signal 103 supplied through the standby channel PROT and distributed from the distribution circuit 11 and a digital signal 104 supplied through the regular channel REG are coincided with each other in the synchronizing switch circuit 6 at the receiving terminal station, instantaneous switching is performed without generation of bit error without using the frame sync signal. In the synchronizing switch circuit 6, the input signals 103 and 104 are respectively N-frequency-divided and converted by frequency division converters into N parallel data. In this case, each of the regular and stand-by N parallel data has a data length of N bits of an original serial data signal. Therefore, if a receiving timing difference between the data signal supplied through the regular channel and that supplied through the stand-by channel falls within the range of +N/2 bits, the timing difference between both the data signals can be absorbed by reading out them in response to a common clock signal, thereby performing synchronizing switching without generation of bit error. The synchronizing switch circuit 6 further includes signal sequence changers respectively connected to output terminals of the frequency division converters, and a bit comparator for comparing output bits from the signal sequence changers. It is determined which one of the two signal sequence changers is operated in accordance with an output from the comparator. As a result, an influence of initial phase instability of frequency dividers of the frequency division circuits can be eliminated without using the frame sync signal.
In recent years, along with spread of digital signal transmission, a zero continuous suppression code such as a BnZS (Bipolar with n Zeros Substitution) code which transmits continuation of n "0"s which replace a substitution code of a specific pattern including a pulse which violates a bipolar code rule of alternately transmitting positive and negative pulses has been adopted as the standard code of the CCITT instead of a conventional bipolar code (which is also called an AMI signal and is a bipolar RZ (Return-to-Zero) code which alternately assigns positive and negative pulses "+A" and "-A" to "1" of a binary code). That is, a B3ZS code and a B6ZS code are already used, and a B8ZS code is planned to be used.
As for the B3ZS code, refer to Item 5 of CCITT RECOMMENDATION G. 703.
In the conventional digital transmission system using a bipolar code, a scrambled signal is normally used. Therefore, even when information is not inputted at all, the multiplexed digital signal 100 input from the digital multiplexing unit as shown in FIG. 1 has many data conversion points, so that no abnormality occurs in an operation of the synchronizing switch circuit 6. However, when the BnZS code is used, no scrambling is performed. Therefore, when the BnZS code is converted into a unipolar code in the B/U converter 2, the substitution code must be decoded to its original code and then transmitted. As a result, when information is not inputted at all, continuation of the same codes "0" or "1" is generated at an output of the B/U converter 2. In this case, since the scrambling for a radio section is also performed in the transmission signal processing circuit 3, no problem is posed in reproduction of bit synchronization or in smoothing of a spectrum in the radio section. However, since an output from the reception signal processing circuit 5 of the receiving terminal station becomes continuation of "0"s or "1"s similar to the input of the transmission signal processing circuit 3, each of the parallel data signals from the frequency division converters of the synchronizing switch circuit 6 becomes continuation of "0"s or "1"s. As a result, a phase shift based on the initial phase instability of the frequency dividers cannot be detected by bit comparison of the comparator. For this reason, when information is not inputted at all, i.e., in a nonload state and when the number of information inputs is small, i.e., in a light load state, a switching time is prolonged to cause an erroneous operation.